Update params

main
nschoe 3 months ago
parent 875bc36414
commit 428477243f

@ -1,7 +1,7 @@
(kicad_pcb (kicad_pcb
(version 20240108) (version 20241229)
(generator "pcbnew") (generator "pcbnew")
(generator_version "8.0") (generator_version "9.0")
(general (general
(thickness 1.5842) (thickness 1.5842)
(legacy_teardrops no) (legacy_teardrops no)
@ -9,41 +9,42 @@
(paper "A4") (paper "A4")
(layers (layers
(0 "F.Cu" signal) (0 "F.Cu" signal)
(1 "In1.Cu" signal) (4 "In1.Cu" power)
(2 "In2.Cu" signal) (6 "In2.Cu" power)
(31 "B.Cu" signal) (2 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive") (9 "F.Adhes" user "F.Adhesive")
(33 "F.Adhes" user "F.Adhesive") (11 "B.Adhes" user "B.Adhesive")
(34 "B.Paste" user) (13 "F.Paste" user)
(35 "F.Paste" user) (15 "B.Paste" user)
(36 "B.SilkS" user "B.Silkscreen") (5 "F.SilkS" user "F.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen") (7 "B.SilkS" user "B.Silkscreen")
(38 "B.Mask" user) (1 "F.Mask" user)
(39 "F.Mask" user) (3 "B.Mask" user)
(40 "Dwgs.User" user "User.Drawings") (17 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments") (19 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1") (21 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2") (23 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user) (25 "Edge.Cuts" user)
(45 "Margin" user) (27 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard") (31 "F.CrtYd" user "F.Courtyard")
(47 "F.CrtYd" user "F.Courtyard") (29 "B.CrtYd" user "B.Courtyard")
(48 "B.Fab" user) (35 "F.Fab" user)
(49 "F.Fab" user) (33 "B.Fab" user)
(50 "User.1" user) (39 "User.1" user)
(51 "User.2" user) (41 "User.2" user)
(52 "User.3" user) (43 "User.3" user)
(53 "User.4" user) (45 "User.4" user)
(54 "User.5" user) (47 "User.5" user)
(55 "User.6" user) (49 "User.6" user)
(56 "User.7" user) (51 "User.7" user)
(57 "User.8" user) (53 "User.8" user)
(58 "User.9" user) (55 "User.9" user)
) )
(setup (setup
(stackup (stackup
(layer "F.SilkS" (layer "F.SilkS"
(type "Top Silk Screen") (type "Top Silk Screen")
(material "Liquid Photo")
) )
(layer "F.Paste" (layer "F.Paste"
(type "Top Solder Paste") (type "Top Solder Paste")
@ -58,6 +59,7 @@
) )
(layer "dielectric 1" (layer "dielectric 1"
(type "prepreg") (type "prepreg")
(color "FR4 natural")
(thickness 0.0994) (thickness 0.0994)
(material "FR4") (material "FR4")
(epsilon_r 4.1) (epsilon_r 4.1)
@ -69,6 +71,7 @@
) )
(layer "dielectric 2" (layer "dielectric 2"
(type "core") (type "core")
(color "FR4 natural")
(thickness 1.265) (thickness 1.265)
(material "FR4") (material "FR4")
(epsilon_r 4.6) (epsilon_r 4.6)
@ -80,6 +83,7 @@
) )
(layer "dielectric 3" (layer "dielectric 3"
(type "prepreg") (type "prepreg")
(color "FR4 natural")
(thickness 0.0994) (thickness 0.0994)
(material "FR4") (material "FR4")
(epsilon_r 4.1) (epsilon_r 4.1)
@ -98,6 +102,7 @@
) )
(layer "B.SilkS" (layer "B.SilkS"
(type "Bottom Silk Screen") (type "Bottom Silk Screen")
(material "Liquid Photo")
) )
(copper_finish "HAL SnPb") (copper_finish "HAL SnPb")
(dielectric_constraints yes) (dielectric_constraints yes)
@ -105,9 +110,10 @@
(pad_to_mask_clearance 0) (pad_to_mask_clearance 0)
(solder_mask_min_width 0.13) (solder_mask_min_width 0.13)
(allow_soldermask_bridges_in_footprints yes) (allow_soldermask_bridges_in_footprints yes)
(tenting front back)
(pcbplotparams (pcbplotparams
(layerselection 0x00010fc_ffffffff) (layerselection 0x00000000_00000000_55555555_5755f5ff)
(plot_on_all_layers_selection 0x0000000_00000000) (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000)
(disableapertmacros no) (disableapertmacros no)
(usegerberextensions no) (usegerberextensions no)
(usegerberattributes yes) (usegerberattributes yes)
@ -117,7 +123,6 @@
(dashed_line_gap_ratio 3.000000) (dashed_line_gap_ratio 3.000000)
(svgprecision 4) (svgprecision 4)
(plotframeref no) (plotframeref no)
(viasonmask no)
(mode 1) (mode 1)
(useauxorigin no) (useauxorigin no)
(hpglpennumber 1) (hpglpennumber 1)
@ -125,16 +130,19 @@
(hpglpendiameter 15.000000) (hpglpendiameter 15.000000)
(pdf_front_fp_property_popups yes) (pdf_front_fp_property_popups yes)
(pdf_back_fp_property_popups yes) (pdf_back_fp_property_popups yes)
(pdf_metadata yes)
(pdf_single_document no)
(dxfpolygonmode yes) (dxfpolygonmode yes)
(dxfimperialunits yes) (dxfimperialunits yes)
(dxfusepcbnewfont yes) (dxfusepcbnewfont yes)
(psnegative no) (psnegative no)
(psa4output no) (psa4output no)
(plotreference yes) (plot_black_and_white yes)
(plotvalue yes)
(plotfptext yes)
(plotinvisibletext no)
(sketchpadsonfab no) (sketchpadsonfab no)
(plotpadnumbers no)
(hidednponfab no)
(sketchdnponfab yes)
(crossoutdnponfab yes)
(subtractmaskfromsilk no) (subtractmaskfromsilk no)
(outputformat 1) (outputformat 1)
(mirror no) (mirror no)
@ -144,4 +152,5 @@
) )
) )
(net 0 "") (net 0 "")
(embedded_fonts no)
) )

@ -10,6 +10,7 @@
"opacity": { "opacity": {
"images": 0.6, "images": 0.6,
"pads": 1.0, "pads": 1.0,
"shapes": 1.0,
"tracks": 1.0, "tracks": 1.0,
"vias": 1.0, "vias": 1.0,
"zones": 0.6 "zones": 0.6
@ -28,43 +29,27 @@
"zones": true "zones": true
}, },
"visible_items": [ "visible_items": [
0, "vias",
1, "footprint_text",
2, "footprint_anchors",
3, "ratsnest",
4, "grid",
5, "footprints_front",
8, "footprints_back",
9, "footprint_values",
10, "footprint_references",
11, "tracks",
12, "drc_errors",
13, "drawing_sheet",
15, "bitmaps",
16, "pads",
17, "zones",
18, "drc_warnings",
19, "locked_item_shadows",
20, "conflict_shadows",
21, "shapes"
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
39,
40
], ],
"visible_layers": "fffffff_ffffffff", "visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
"zone_display_mode": 0 "zone_display_mode": 0
}, },
"git": { "git": {
@ -75,9 +60,78 @@
}, },
"meta": { "meta": {
"filename": "JLCPCB-4L-3313.kicad_prl", "filename": "JLCPCB-4L-3313.kicad_prl",
"version": 3 "version": 5
},
"net_inspector_panel": {
"col_hidden": [
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false
],
"col_order": [
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"col_widths": [
156,
141,
103,
71,
103,
103,
103,
74,
103,
103,
103,
103
],
"custom_group_rules": [],
"expanded_rows": [],
"filter_by_net_name": true,
"filter_by_netclass": true,
"filter_text": "",
"group_by_constraint": false,
"group_by_netclass": false,
"show_unconnected_nets": false,
"show_zero_pad_nets": false,
"sort_ascending": true,
"sorting_column": 0
}, },
"open_jobsets": [],
"project": { "project": {
"files": [] "files": []
},
"schematic": {
"selection_filter": {
"graphics": true,
"images": true,
"labels": true,
"lockedItems": false,
"otherItems": true,
"pins": true,
"symbols": true,
"text": true,
"wires": true
}
} }
} }

@ -69,16 +69,19 @@
"copper_edge_clearance": "error", "copper_edge_clearance": "error",
"copper_sliver": "warning", "copper_sliver": "warning",
"courtyards_overlap": "error", "courtyards_overlap": "error",
"creepage": "error",
"diff_pair_gap_out_of_range": "error", "diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error", "diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error", "drill_out_of_range": "error",
"duplicate_footprints": "warning", "duplicate_footprints": "warning",
"extra_footprint": "warning", "extra_footprint": "warning",
"footprint": "error", "footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_mismatch": "warning", "footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore", "footprint_type_mismatch": "ignore",
"hole_clearance": "error", "hole_clearance": "error",
"hole_near_hole": "error", "hole_near_hole": "error",
"hole_to_hole": "error",
"holes_co_located": "warning", "holes_co_located": "warning",
"invalid_outline": "error", "invalid_outline": "error",
"isolated_copper": "warning", "isolated_copper": "warning",
@ -89,9 +92,11 @@
"lib_footprint_mismatch": "warning", "lib_footprint_mismatch": "warning",
"malformed_courtyard": "error", "malformed_courtyard": "error",
"microvia_drill_out_of_range": "error", "microvia_drill_out_of_range": "error",
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "ignore", "missing_courtyard": "ignore",
"missing_footprint": "warning", "missing_footprint": "warning",
"net_conflict": "warning", "net_conflict": "warning",
"nonmirrored_text_on_back_layer": "warning",
"npth_inside_courtyard": "ignore", "npth_inside_courtyard": "ignore",
"padstack": "warning", "padstack": "warning",
"pth_inside_courtyard": "ignore", "pth_inside_courtyard": "ignore",
@ -103,10 +108,13 @@
"solder_mask_bridge": "error", "solder_mask_bridge": "error",
"starved_thermal": "error", "starved_thermal": "error",
"text_height": "warning", "text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning", "text_thickness": "warning",
"through_hole_pad_without_hole": "error", "through_hole_pad_without_hole": "error",
"too_many_vias": "error", "too_many_vias": "error",
"track_angle": "error",
"track_dangling": "warning", "track_dangling": "warning",
"track_segment_length": "error",
"track_width": "error", "track_width": "error",
"tracks_crossing": "error", "tracks_crossing": "error",
"unconnected_items": "error", "unconnected_items": "error",
@ -119,6 +127,7 @@
"min_clearance": 0.09, "min_clearance": 0.09,
"min_connection": 0.09, "min_connection": 0.09,
"min_copper_edge_clearance": 0.2, "min_copper_edge_clearance": 0.2,
"min_groove_width": 0.0,
"min_hole_clearance": 0.2, "min_hole_clearance": 0.2,
"min_hole_to_hole": 0.2, "min_hole_to_hole": 0.2,
"min_microvia_diameter": 0.2, "min_microvia_diameter": 0.2,
@ -130,7 +139,7 @@
"min_through_hole_diameter": 0.15, "min_through_hole_diameter": 0.15,
"min_track_width": 0.09, "min_track_width": 0.09,
"min_via_annular_width": 0.15, "min_via_annular_width": 0.15,
"min_via_diameter": 0.35, "min_via_diameter": 0.25,
"solder_mask_clearance": 0.0, "solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0, "solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.05, "solder_mask_to_copper_clearance": 0.05,
@ -138,10 +147,11 @@
}, },
"teardrop_options": [ "teardrop_options": [
{ {
"td_onpadsmd": true, "td_onpthpad": true,
"td_onroundshapesonly": false, "td_onroundshapesonly": false,
"td_onsmdpad": true,
"td_ontrackend": false, "td_ontrackend": false,
"td_onviapad": true "td_onvia": true
} }
], ],
"teardrop_parameters": [ "teardrop_parameters": [
@ -220,8 +230,8 @@
"drill": 0.0 "drill": 0.0
}, },
{ {
"diameter": 0.4, "diameter": 0.35,
"drill": 0.3 "drill": 0.2
}, },
{ {
"diameter": 0.45, "diameter": 0.45,
@ -245,6 +255,7 @@
"mfg": "", "mfg": "",
"mpn": "" "mpn": ""
}, },
"layer_pairs": [],
"layer_presets": [], "layer_presets": [],
"viewports": [] "viewports": []
}, },
@ -439,10 +450,15 @@
"duplicate_sheet_names": "error", "duplicate_sheet_names": "error",
"endpoint_off_grid": "warning", "endpoint_off_grid": "warning",
"extra_units": "error", "extra_units": "error",
"footprint_filter": "ignore",
"footprint_link_issues": "warning",
"four_way_junction": "ignore",
"global_label_dangling": "warning", "global_label_dangling": "warning",
"hier_label_mismatch": "error", "hier_label_mismatch": "error",
"label_dangling": "error", "label_dangling": "error",
"label_multiple_wires": "warning",
"lib_symbol_issues": "warning", "lib_symbol_issues": "warning",
"lib_symbol_mismatch": "warning",
"missing_bidi_pin": "warning", "missing_bidi_pin": "warning",
"missing_input_pin": "warning", "missing_input_pin": "warning",
"missing_power_pin": "error", "missing_power_pin": "error",
@ -455,9 +471,14 @@
"pin_not_driven": "error", "pin_not_driven": "error",
"pin_to_pin": "error", "pin_to_pin": "error",
"power_pin_not_driven": "error", "power_pin_not_driven": "error",
"same_local_global_label": "warning",
"similar_label_and_power": "warning",
"similar_labels": "warning", "similar_labels": "warning",
"similar_power": "warning",
"simulation_model_issue": "ignore", "simulation_model_issue": "ignore",
"single_global_label": "ignore",
"unannotated": "error", "unannotated": "error",
"unconnected_wire_endpoint": "warning",
"unit_value_mismatch": "error", "unit_value_mismatch": "error",
"unresolved_variable": "error", "unresolved_variable": "error",
"wire_dangling": "error" "wire_dangling": "error"
@ -469,7 +490,7 @@
}, },
"meta": { "meta": {
"filename": "JLCPCB-4L-3313.kicad_pro", "filename": "JLCPCB-4L-3313.kicad_pro",
"version": 1 "version": 3
}, },
"net_settings": { "net_settings": {
"classes": [ "classes": [
@ -484,6 +505,7 @@
"microvia_drill": 0.1, "microvia_drill": 0.1,
"name": "Default", "name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15, "track_width": 0.15,
"via_diameter": 0.5, "via_diameter": 0.5,
@ -494,39 +516,52 @@
"bus_width": 12, "bus_width": 12,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.2, "diff_pair_gap": 0.2,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.15, "diff_pair_width": 0.15,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.3, "microvia_diameter": 0.3,
"microvia_drill": 0.1, "microvia_drill": 0.1,
"name": "IC Power", "name": "IC Power",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3, "track_width": 0.25,
"via_diameter": 0.5, "via_diameter": 0.5,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 6 "wire_width": 6
}, },
{
"bus_width": 12,
"clearance": 0.2,
"line_style": 0,
"name": "RF 50Ω",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.183776,
"via_diameter": 0.45,
"via_drill": 0.2,
"wire_width": 6
},
{ {
"bus_width": 12, "bus_width": 12,
"clearance": 0.15, "clearance": 0.15,
"diff_pair_gap": 0.1016, "diff_pair_gap": 0.1016,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1795, "diff_pair_width": 0.1795,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.3, "microvia_diameter": 0.3,
"microvia_drill": 0.1, "microvia_drill": 0.1,
"name": "USB 90Ω", "name": "USB 90Ω",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2,
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15, "track_width": 0.15,
"via_diameter": 0.35, "via_diameter": 0.45,
"via_drill": 0.2, "via_drill": 0.2,
"wire_width": 6 "wire_width": 6
} }
], ],
"meta": { "meta": {
"version": 3 "version": 4
}, },
"net_colors": null, "net_colors": null,
"netclass_assignments": null, "netclass_assignments": null,
@ -546,6 +581,18 @@
{ {
"netclass": "IC Power", "netclass": "IC Power",
"pattern": "GND" "pattern": "GND"
},
{
"netclass": "IC Power",
"pattern": "+2V8"
},
{
"netclass": "USB 90Ω",
"pattern": "USB_D-"
},
{
"netclass": "USB 90Ω",
"pattern": "USB_D+"
} }
] ]
}, },
@ -619,6 +666,7 @@
], ],
"filter_string": "", "filter_string": "",
"group_symbols": true, "group_symbols": true,
"include_excluded_from_bom": false,
"name": "Grouped By Value", "name": "Grouped By Value",
"sort_asc": true, "sort_asc": true,
"sort_field": "Reference" "sort_field": "Reference"
@ -653,6 +701,7 @@
"net_format_name": "", "net_format_name": "",
"page_layout_descr_file": "", "page_layout_descr_file": "",
"plot_directory": "", "plot_directory": "",
"space_save_all_events": true,
"spice_current_sheet_as_root": false, "spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"", "spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true, "spice_model_current_sheet_as_root": true,

@ -1,7 +1,7 @@
(kicad_sch (kicad_sch
(version 20231120) (version 20250114)
(generator "eeschema") (generator "eeschema")
(generator_version "8.0") (generator_version "9.0")
(uuid "71ceb321-9393-471b-91d3-3d258e11ac9f") (uuid "71ceb321-9393-471b-91d3-3d258e11ac9f")
(paper "A4") (paper "A4")
(lib_symbols) (lib_symbols)
@ -10,4 +10,5 @@
(page "1") (page "1")
) )
) )
(embedded_fonts no)
) )

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