From 9e8bd334c3aefda122dcfbb467d3a3068f02ec48 Mon Sep 17 00:00:00 2001
From: nschoe <nschoe@protonmail.com>
Date: Fri, 14 Jun 2024 17:57:41 +0200
Subject: [PATCH] Fix vias holes predefined sizes

---
 JLCPCB-4L-3313.kicad_pcb | 2 +-
 JLCPCB-4L-3313.kicad_pro | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/JLCPCB-4L-3313.kicad_pcb b/JLCPCB-4L-3313.kicad_pcb
index 187ce3c..1b93492 100644
--- a/JLCPCB-4L-3313.kicad_pcb
+++ b/JLCPCB-4L-3313.kicad_pcb
@@ -144,4 +144,4 @@
 		)
 	)
 	(net 0 "")
-)
\ No newline at end of file
+)
diff --git a/JLCPCB-4L-3313.kicad_pro b/JLCPCB-4L-3313.kicad_pro
index 60dcc72..c641020 100644
--- a/JLCPCB-4L-3313.kicad_pro
+++ b/JLCPCB-4L-3313.kicad_pro
@@ -79,6 +79,7 @@
         "footprint_type_mismatch": "ignore",
         "hole_clearance": "error",
         "hole_near_hole": "error",
+        "holes_co_located": "warning",
         "invalid_outline": "error",
         "isolated_copper": "warning",
         "item_on_disabled_layer": "error",
@@ -218,7 +219,11 @@
           "drill": 0.0
         },
         {
-          "diameter": 0.35,
+          "diameter": 0.4,
+          "drill": 0.3
+        },
+        {
+          "diameter": 0.45,
           "drill": 0.2
         },
         {