From 59b5c65c370b6bfbcbcc17f698ed8b7762ee2195 Mon Sep 17 00:00:00 2001 From: nschoe Date: Mon, 12 Feb 2024 15:45:45 +0100 Subject: [PATCH] Setup constraints for JLCPCB fab, 2 layer board --- JLCPCB-2L.kicad_pcb | 94 +++++++++++++++ JLCPCB-2L.kicad_prl | 77 ++++++++++++ JLCPCB-2L.kicad_pro | 276 ++++++++++++++++++++++++++++++++++++++++++++ JLCPCB-2L.kicad_sch | 5 + meta/info.html | 12 ++ meta/tmp.html | 47 ++++++++ 6 files changed, 511 insertions(+) create mode 100644 JLCPCB-2L.kicad_pcb create mode 100644 JLCPCB-2L.kicad_prl create mode 100644 JLCPCB-2L.kicad_pro create mode 100644 JLCPCB-2L.kicad_sch create mode 100644 meta/info.html create mode 100644 meta/tmp.html diff --git a/JLCPCB-2L.kicad_pcb b/JLCPCB-2L.kicad_pcb new file mode 100644 index 0000000..b8a511f --- /dev/null +++ b/JLCPCB-2L.kicad_pcb @@ -0,0 +1,94 @@ +(kicad_pcb (version 20221018) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen")) + (copper_finish "HAL SnPb") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0.038) + (solder_mask_min_width 0.13) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + +) diff --git a/JLCPCB-2L.kicad_prl b/JLCPCB-2L.kicad_prl new file mode 100644 index 0000000..4ed6303 --- /dev/null +++ b/JLCPCB-2L.kicad_prl @@ -0,0 +1,77 @@ +{ + "board": { + "active_layer": 0, + "active_layer_preset": "All Layers", + "auto_track_width": true, + "hidden_netclasses": [], + "hidden_nets": [], + "high_contrast_mode": 0, + "net_color_mode": 1, + "opacity": { + "images": 0.6, + "pads": 1.0, + "tracks": 1.0, + "vias": 1.0, + "zones": 0.6 + }, + "selection_filter": { + "dimensions": true, + "footprints": true, + "graphics": true, + "keepouts": true, + "lockedItems": false, + "otherItems": true, + "pads": true, + "text": true, + "tracks": true, + "vias": true, + "zones": true + }, + "visible_items": [ + 0, + 1, + 2, + 3, + 4, + 5, + 8, + 9, + 10, + 11, + 12, + 13, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 32, + 33, + 34, + 35, + 36, + 39, + 40 + ], + "visible_layers": "fffffff_ffffffff", + "zone_display_mode": 0 + }, + "meta": { + "filename": "JLCPCB-2L.kicad_prl", + "version": 3 + }, + "project": { + "files": [] + } +} diff --git a/JLCPCB-2L.kicad_pro b/JLCPCB-2L.kicad_pro new file mode 100644 index 0000000..cbb57c8 --- /dev/null +++ b/JLCPCB-2L.kicad_pro @@ -0,0 +1,276 @@ +{ + "board": { + "3dviewports": [], + "design_settings": { + "defaults": { + "board_outline_line_width": 0.09999999999999999, + "copper_line_width": 0.19999999999999998, + "copper_text_italic": false, + "copper_text_size_h": 1.5, + "copper_text_size_v": 1.5, + "copper_text_thickness": 0.3, + "copper_text_upright": false, + "courtyard_line_width": 0.049999999999999996, + "dimension_precision": 4, + "dimension_units": 3, + "dimensions": { + "arrow_length": 1270000, + "extension_offset": 500000, + "keep_text_aligned": true, + "suppress_zeroes": false, + "text_position": 0, + "units_format": 1 + }, + "fab_line_width": 0.09999999999999999, + "fab_text_italic": false, + "fab_text_size_h": 1.0, + "fab_text_size_v": 1.0, + "fab_text_thickness": 0.15, + "fab_text_upright": false, + "other_line_width": 0.15, + "other_text_italic": false, + "other_text_size_h": 1.0, + "other_text_size_v": 1.0, + "other_text_thickness": 0.15, + "other_text_upright": false, + "pads": { + "drill": 0.762, + "height": 1.524, + "width": 1.524 + }, + "silk_line_width": 0.15, + "silk_text_italic": false, + "silk_text_size_h": 1.0, + "silk_text_size_v": 1.0, + "silk_text_thickness": 0.15, + "silk_text_upright": false, + "zones": { + "min_clearance": 0.5 + } + }, + "diff_pair_dimensions": [ + { + "gap": 0.0, + "via_gap": 0.0, + "width": 0.0 + } + ], + "drc_exclusions": [], + "meta": { + "version": 2 + }, + "rule_severities": { + "annular_width": "error", + "clearance": "error", + "connection_width": "warning", + "copper_edge_clearance": "error", + "copper_sliver": "warning", + "courtyards_overlap": "error", + "diff_pair_gap_out_of_range": "error", + "diff_pair_uncoupled_length_too_long": "error", + "drill_out_of_range": "error", + "duplicate_footprints": "warning", + "extra_footprint": "warning", + "footprint": "error", + "footprint_type_mismatch": "ignore", + "hole_clearance": "error", + "hole_near_hole": "error", + "invalid_outline": "error", + "isolated_copper": "warning", + "item_on_disabled_layer": "error", + "items_not_allowed": "error", + "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "net_conflict": "warning", + "npth_inside_courtyard": "ignore", + "padstack": "warning", + "pth_inside_courtyard": "ignore", + "shorting_items": "error", + "silk_edge_clearance": "warning", + "silk_over_copper": "warning", + "silk_overlap": "warning", + "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_thickness": "warning", + "through_hole_pad_without_hole": "error", + "too_many_vias": "error", + "track_dangling": "warning", + "track_width": "error", + "tracks_crossing": "error", + "unconnected_items": "error", + "unresolved_variable": "error", + "via_dangling": "warning", + "zones_intersect": "error" + }, + "rules": { + "max_error": 0.005, + "min_clearance": 0.127, + "min_connection": 0.127, + "min_copper_edge_clearance": 0.3, + "min_hole_clearance": 0.25, + "min_hole_to_hole": 0.25, + "min_microvia_diameter": 0.19999999999999998, + "min_microvia_drill": 0.09999999999999999, + "min_resolved_spokes": 2, + "min_silk_clearance": 0.0, + "min_text_height": 0.7999999999999999, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.3, + "min_track_width": 0.127, + "min_via_annular_width": 0.13, + "min_via_diameter": 0.5, + "solder_mask_clearance": 0.0, + "solder_mask_min_width": 0.0, + "solder_mask_to_copper_clearance": 0.0, + "use_height_for_length_calcs": true + }, + "teardrop_options": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 5, + "td_on_pad_in_zone": false, + "td_onpadsmd": true, + "td_onroundshapesonly": false, + "td_ontrackend": false, + "td_onviapad": true + } + ], + "teardrop_parameters": [ + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], + "track_widths": [ + 0.0, + 0.127, + 0.15, + 0.2, + 0.25, + 0.3, + 0.5, + 1.0 + ], + "via_dimensions": [ + { + "diameter": 0.0, + "drill": 0.0 + }, + { + "diameter": 0.5, + "drill": 0.3 + }, + { + "diameter": 0.6, + "drill": 0.4 + } + ], + "zones_allow_external_fillets": false + }, + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "JLCPCB-2L.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.2, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.15, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.25, + "via_diameter": 0.6, + "via_drill": 0.4, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.2, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.15, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "IC Power", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.3, + "via_diameter": 0.6, + "via_drill": 0.4, + "wire_width": 6 + } + ], + "meta": { + "version": 3 + }, + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [] + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "legacy_lib_dir": "", + "legacy_lib_list": [] + }, + "sheets": [], + "text_variables": {} +} diff --git a/JLCPCB-2L.kicad_sch b/JLCPCB-2L.kicad_sch new file mode 100644 index 0000000..2e2aa2f --- /dev/null +++ b/JLCPCB-2L.kicad_sch @@ -0,0 +1,5 @@ +(kicad_sch (version 20230121) (generator eeschema) + (paper "A4") + (lib_symbols) + (symbol_instances) +) diff --git a/meta/info.html b/meta/info.html new file mode 100644 index 0000000..cb9eee4 --- /dev/null +++ b/meta/info.html @@ -0,0 +1,12 @@ + + + JLCPCB 2-Layer Board + + +

JLCPCB 2-Layer Board

+

+ Contains board settings and constraints for PCB Assembly at JLCPCB for a 2-layer board.
+ Also add some pre-defined common track & via dimensions. +

+ + diff --git a/meta/tmp.html b/meta/tmp.html new file mode 100644 index 0000000..638db0c --- /dev/null +++ b/meta/tmp.html @@ -0,0 +1,47 @@ + + + Raspberry Pi HAT + + +

Raspberry Pi HAT

+

40-pin Expansion Board

+ +

+ This project template forms the basis of an expansion board (HAT) for the Raspberry Pi single board computers with a 40-pin GPIO header. +
+ This includes the following models:
+

+

+ +

+ Note: for the Pi Zero (W) or smaller designs, see the RaspberryPi-uHAT template. +

+ +

+ This project includes a PCB edge set according to the Raspberry Pi HAT Mechanical Specification with connectors placed correctly to align the two boards. An alternate edge is included on the User.Drawings layer for the use with an SMT connector. Cutouts have also been defined for the camera and the display cables. +

+ +

+ The schematic includes an ID EEPROM chip along with the necessary support components. It does not specify footprints for the ID EEPROM. It is up to the user to choose an appropriate EEPROM chip and footprints. +

+ +

+ The official Raspberry Pi HAT Specification includes additional information and a design guide. +

+ +

+ +

(c) 2021 Caleb Reister

+ +

+ Adapted from the raspberrypi-gpio-40pin template:
+ (c) 2016 Ashton Johnson
+ (c) 2016 Kicad Developers +

+ +